The present invention relates to clock signal control for use in integrated circuits; and, more particularly, to a clocking mechanism that does not require added datapath logic or added skew management between clock domains and that provides launch and capture product clock capability for the testing of product logic designs having multiple operating frequencies and/or operation using multiple clock edges.
Advances in integrated circuits have enhanced the ability to integrate increasingly more circuits on a single chip. As the circuit complexity on a chip increases, so does the need to thoroughly test the circuits. A general solution to the problem of testing integrated circuits is to embed test circuitry on the chip itself. One such methodology is commonly known as xe2x80x9cLogic built-In Self testxe2x80x9d (LBIST) and utilizes what is commonly referred to as xe2x80x9cSelf-Test Using Multiple Signal Registers and pseudo-Random Pattern Generatorsxe2x80x9d (STUMP) architecture. LBIST circuits typically test a circuit""s function and provide a failure indication if the circuit is not functioning properly.
Ideally, such testing systems should provide at least three functional modes which include: 1) an operational mode that allows the chip to perform in its intended manner, 2) a system test mode that allows for internal system-based testing; and 3) an external test mode that allows for external input of test data through the chip""s pins.
As the number of circuits and logical functions integrated onto a single chip increases, the complexity and sophistication of on-chip LBIST circuits and desired LBIST performance features also increases. One problem that arises in such design relates to clock control when attempting to test the circuits at their operational speed. Specifically, known methods for clock control and LBIST-STUMP architecture lead to significant intrusion (e.g., delay, latency, duty cycle alteration) of the system clock signal and either require system data path reduction for at-speed scan operation or multiple system clock trees with critical balancing of the timing between the trees.
Edge-triggered design having STUMPs based LBIST capability require a clock control structure for switching between system operational mode and test mode, and for performing a master and slave operation in one system cycle. Such systems require that data be launched from the slave to the combinational logic to be tested, and to capture the result in the master of the next stage Known methods for achieving such control use logic manipulation of the oscillator signal prior to the clock powering logic. Such systems either use edge-triggered flip-flop with scan multiplexing to manipulate oscillator edges for launch and capture control, or convert the system clock signal into a master and slave clock and separately enable these two clocks for system LBIST test or scan operation. These techniques, however, have significant disadvantages.
Edge-triggered flip-flop clock systems using a straight forward application of edge-triggered design methods present significant intrusion on the oscillator wave form. U.S. Pat. No. 4,961,013 issued to Obermyer, Jr. et al. xe2x80x9cApparatus for Generation for Scan Control Signals for Initialization and Diagnosis of Circuitry in a Computer,xe2x80x9d discloses such a system. Such systems typically utilize OR and XOR gates, adding delay-latency and potential duty cycle alteration due to any rise/fall time imbalance. Furthermore, at-speed scan operation requires system data path reduction caused by data port multiplexer delay.
Some systems are designed using multiple clocks, whereby the set of latches or flip-flops receiving a particular clock can be called a clock domain, thus the system has multiple clock domains. Testing of such systems has to deal with the issue of reliably testing the paths between the domains, particularly when the domains"" clocks do not operate synchronously with each other. Known methods requiring either
1. the addition of data path logic, at the cost of circuit area, logic design complexity, and performance impact, for the purpose of synchronizing these paths during test operation, or
2. Blocking these paths during the test operation, resulting In the loss of testing coverage and, like 1., adding circuit area, complexity and impacting performance.
Although various patents have attempted to address some of these issues, none provide an efficient means of overcoming the above-identified problems.
Therefore, there is a need for simplified clocking mechanism that provides launch and capture product capability for the testing of product logic, for designs having multiple operating frequencies and/or multiple operation clock edges, that does not require added datapath logic or added skew management between clock domains. All of the above references are incorporated herein by reference.
It is, therefore, a primary object of the present invention to provide a generic clocking mechanism that can be applied to any clock-based logic design.
In accordance with the present invention, there is provided an integrated circuit comprising: a clock controller including a plurality of programmable clock templates; a plurality of logic domains, each operating based on clocks having different clocks and/or on different edge of the clocks and operable asynchronously with respect to the others of said logic domains; and a system clock distributed to the logic domains and to the clock controller, each logic domain generating master/slave signals in response to the received system clock, each of the clock templates distributing gating signals to at least one corresponding logic domain, the gating signals selectively gating the generated master/slave signals for distribution throughout said at least one corresponding logic domain.